This invention relates to clock generator circuits, and, more particularly, to clock generator circuits used to apply properly phased clock signals to multiple clocked devices.
Periodic clock signals are for a wide variety of purposes in electronic systems, such as memory devices. Clock signals are typically generated by an oscillator, but clock signals generated by an oscillator may have properties that make them unsuitable for some purposes. For example, such clock signals may exhibit excessive phase jitter, i.e., variations in the phase or timing of the clock signal. While phase jitter may not be a problem in many applications, in some applications where timing in a circuit must be precisely controlled, phase jitter can be unacceptable.
On approach to reducing phase jitter is to process the clock signal with a locked-loop, such as a phase-lock loop or a delay-lock loop. The dynamics of feedback in the loop can be controlled, such as by low-pass filtering the loop, so that a processed clock signal generated by the locked-loop has relatively little phase jitter.
Processing a clock signal using a locked-loop provides acceptable performance in applications where the clock signal is applied to a single circuit or relatively few circuits. However, problems can develop if the processed clock signal is applied to a large number of clocked circuits. These problems are essentially twofold. First, it is generally not possible to place the circuits to which the processed clock signal is applied the same distance from the locked-loop. Consequently, transitions of the clock signal can arrive at each of the circuits at different times. Yet the major function of the clock signal is to ensure that signals in all of the circuits are registered at the same time. This problem has been recognized, and attempts have been made to solve it. One approach, for example, is shown in FIG. 1. A clock generator circuit 10 includes a driver circuit 16 that receives a pair of complimentary clock signals CLK and CLK*. The driver circuit 16 converts the complimentary clock signals CLK and CLK* into a single-ended clock signal that is applied to a phase-lock loop 20. The phase-lock loop 20 generates a processed clock signal CLK-P that is applied to several driver circuits 24. The first driver circuit 24a outputs a complimentary pair of clock signals CLK-OUT and CLK-OUT* that are used as complimentary feedback signals. These complimentary feedback signals are applied to a driver circuit 26 that generates a single-ended feedback signal, which is applied to a feedback input of the phase-lock loop 20.
The remaining driver circuits 24b-k output complimentary clock signals CLK-OUT and CLK-OUT* to respective clocked circuits 28b-k through respective pairs of conductors 30b-k. In the event the clock generator circuit 10 is used, for example, in a memory device, the circuits 28b-k may be memory arrays, although the circuits 28b-k may instead be any type of circuit found in memory devices. Also, of course, the clock generator circuit 10 may be used in devices other than memory devices.
The clock generator circuit 10, the clocked circuits 28 and the conductors 30 are preferably fabricated on a common substrate 34. In the case of an integrated circuit, the substrate 34 will normally be a semiconductor substrate, such as a silicon die. However, the components shown in FIG. 10 may instead be discrete circuits, in which case the substrate 34 may instead be a printed circuit board, for example.
As mentioned earlier, one of the problems that can develop if the processed clock signals are applied to a large number of circuits is the pairs of clock signals CLK-OUT and CLK-OUT* may arrive at respective circuits 28b-k at different times. To solve this problem, the conductors 30b-k coupling the clock signals CLK-OUT to the circuits 28b-k, respectively, are routed as shown in FIG. 2.
As shown in FIG. 2, all of the conductors 30b-k coupling the drivers 24b-k (FIG. 1) to the circuits 28b-k all have the same length. Using this approach, the conductor 30b coupling the clock signals CLK-OUT and CLK-OUT* to the circuit 28b farthest from the clock generator circuit 10 is relatively direct, while the conductors 30k coupling the clock signals CLK-OUT and CLK-OUT* to the circuit 28k closest to the clock generator circuit 10 are very serpentine. Although this approach is effective to equalize the times the clock signals CLK-OUT and CLK-OUT* are applied to the respective circuits 28, the amount of area consumed by the serpentine conductors 30 can be very problematic in some applications. For example, if the clock generator circuit 10, conductors 30 and clocked circuits 28 are fabricated on a semiconductor die, the serpentine conductors 30 can substantially increase the required size of the semiconductor die and hence the cost of an integrated circuit using the clock generator circuit 10.
The second problem that can develop if the processed clock signal is applied to a large number of clocked circuits 28 is the creation of phase jitter, which is the very problem the use of the phase-lock loop 20 was intended to avoid. With reference to FIG. 1, on each transition of the processed clock signal CLK-P, all of the driver circuits 24a-k switch at the same time, thereby drawing current at the same time. The result is a transient increase in current on each transition of the processed clock signal CLK-P, which generally produces a transient decrease in voltage of the power supplied to the phase-lock loop 20. For most phase-lock loop designs, the voltage transient causes a transient increase or decrease in the phase of the processed clock signal CLK-P produced by the locked-loop 20. As mentioned above, this transient increase or decrease in the phase of the processed clock signal CLK-P constitutes phase jitter. As mentioned previously, this phase jitter defeats the major reason for using the phase-lock loop 20, i.e., to reduce phase jitter.
There is therefore a need for a clock generator circuit that can provide a clock signal having reduced phase jitter to several circuits without consuming significant substrate area by routing the clock signals to the circuits through serpentine conductor paths.
A clock generator circuit and method is used to apply respective clock signals to a plurality of clocked circuits. A processed clock signal is generated by applying an input clock signal to a locked-loop, such as a phase-lock loop. The processed clock signal is delayed a plurality of respective delay times by a suitable delay circuit, such as a plurality of serially coupled delay elements, to generate a plurality of delayed clock signals. Each of the delayed clock signal is coupled through a respective signal path to a respective clocked circuit. The length of the signal paths through which each of the delayed clock signals is coupled is inversely proportional to the delay of the delayed clock signal that is coupled through the signal path. As a result, the delayed clock signals are applied to respective clocked circuits at substantially the same time.